1. Field of the Invention
The present invention relates to a signal processing apparatus, and more particularly, it relates to a signal processing apparatus which receives an analog signal to convert the same into a digital signal and processes the digital signal to re-convert the processed digital signal into an analog signal, to thereby output the same.
2. Description of the Background Art
FIG. 1A is a block diagram showing a conventional signal processing apparatus which is formed by current integration type adaptive delta modulators and a data processor. This signal processing apparatus serves as an analog delay system, which can be employed for processing a sound signal such as an echo signal. An analog sound signal is inputted in an analog signal input terminal 1. A current integration type adaptive delta modulator 2 modulates the analog signal received in the analog signal input terminal 1 into a digital signal. A data processor 3 is supplied with the digital signal from the current integration type adaptive delta modulator 2, to perform delay processing for echo on the digital signal and output the same. As shown in FIG. 1B, the data processor 3 is formed by a logic circuit 3A and a memory 3B. A data processing mode change command is supplied to the data processor 3 through a data processing mode change command terminal 4. When the data processing mode change command is supplied, a working area of the memory 3B included in the data processor 3 is changed. A current integration type adaptive delta demodulator 5 demodulates the digital signal, which is subjected to the delay processing for echo, into an analog signal. The analog signal outputted from the current integration type adaptive delta demodulator 5 is extracted from an analog signal output terminal 6.
FIG. 2 illustrates waveforms of respective signals in normal operation, and FIG. 3 illustrates waveforms of the respective signals in an initial state upon power supply.
With reference to FIG. 2, operation in a normal state will now be described. It is assumed here that an analog signal A shown in FIG. 2 is inputted in the analog signal input terminal 1. This analog signal A is modulated into a digital signal by the current integration type adaptive delta modulator 2, to be supplied to the data processor 3. The data processor 3 employs a constant area of the memory 3B to repeat reading and writing of data in a FIFO system through the logic circuit 3A. A delay time is decided depending on the working area of the memory 3B. Thus, the digital signal is subjected to delay processing for echo. The current integration type adaptive delta demodulator 5 demodulates a digital signal C thus subjected to delay processing into an analog signal D, to output the same from the analog signal output terminal 6. It is assumed here that a data processing mode change command B is inputted from the data processing mode change command terminal 4 to the data processor 3 at a time t1. In response to this, the data processing mode of the data processor 3 is changed. It is assumed that the working area of the memory 3B included in the data processor 3 is expanded as the data processing mode changes, for example. Immediately upon supply of the data processing mode change command B, data are read at random since no correct data are written in the expanded working area of the memory 3B. A constant time is required to thereafter write/read correct data in/from the working area. In other words, output data C of the data processor 3 are instable during an interval between times t1 and t2 shown in FIG. 2. In the interval between the times t1 and t2, the instable data C are demodulated by the current integration type adaptive delta demodulator 5 into the analog signal D, to be outputted from the analog signal output terminal. Thus, an abnormal analog signal D is outputted in the interval between the times t1 and t2, to cause noise etc. After the data C are stabilized at the time t2, a normal analog signal D is outputted from the analog signal output terminal 6.
Operation in an initial state upon power supply will now be described with reference to FIG. 3. Also in the initial state upon power supply, no correct data are written in the working area of the memory 3B, similarly to the above. Thus, a lapse of a constant interval (from time 0 to time t3) is required for writing and reading correct data. Also in the initial state, instable data C are converted into the analog signal D by the current integration type adaptive delta demodulator 5 in the interval between the times 0 and t3, to be outputted. Thus, an abnormal analog signal D is outputted in the interval between the times 0 and t3, to cause noise etc. After the data C are stabilized at the time t3, a normal analog signal D is outputted.
In the conventional signal processing apparatus of the aforementioned structure, the current integration type adaptive delta demodulator 5 converts the insufficiently stabilized data C into the analog signal D to output the same, whereby noise or the like is caused by such an abnormal analog signal. A similar problem is caused also in an initial state upon power supply, since the current integration type adaptive delta demodulator 5 converts the insufficiently stabilized data into the analog signal D to output the same also in this case.